pretty much bang on explination nozzer.
since the clocks are divided down from a single crystal the different frequecies required 18.432,9.216 and 4.608 are routed through different numbers of digital gates. the downside is that if the gates are not chosen precisely enough for the job then the clock is out of phase across the 3 ranges by multiples of the gates propogation delays, this can cause a huge difference in the efectiveness of the glitch types. this can be worked around to a small degree by impedance matching the card using the pot but only with a timing curcuit that has halfway decent.
so atmel says glitch on low clock, but if the delays inherent in the timing curcuit are too severe then the low clock may be as much as a half atmel cycle out of phase with the card clock actual. This would have a fundamental effect on glitchtype effectiveness. especially i reckon on types 6 to 10.
.1 to .6volt drops across the vcc supplies of one or more of the three main clocking components ic's 1,2 and 3 would provide some relative adjustability again somewhat limited of course.
also bare in mind that nexus and afaik t911 are configured such that the card vcc is fed via the lm358 op amp which in turn is fed by the 5v regulator. This is generally different to clasical glitcher design in that the generally accepted method would be to feed the op amp with the unregulated supply, this can avoid the scenario where rsts are seen as a result of power drain across the curcuit instead of actually glitching activity as it is often neccessary to run a card on the threshold of its ability to function in order to render it more susceptable to glitching.
regards tbc